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A Method Of High Level Synthesis In Integrated Circuit Design Using Application Specific Bit Widths

Submitted by Jayshree on Thu, 05/29/2025 - 12:51
Patent Number
201911028124
Patent Status
Published
Campus
Pilani Campus
Department
Electrical & Electronics Engineering
Inventors
Dr. Abhijit Rameshwar Asati , Dr. Asati Abhijit R / Prateek Sikka / Dr. Chandra Shekhar
Granted On
Thu, 01/01/1970 - 12:00

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